Thin film transistor

ABSTRACT

A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of application Ser. No. 10/906,041, filed on Feb. 1, 2005, which is now allowed and all disclosures of the application are incorporated herewith by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a thin film transistor.

2. Description of Related Art

In a device, a switch is formed for controlling the operation of the device. As to an active display device, a thin film transistor (TFT) is generally made as a switch. Based on the material of the channel of thin film transistors, there are two types of TFT: amorphous silicon (a-Si) thin film transistor and polysilicon thin film transistor. A polysilicon thin film transistor has lower consuming power and higher electromigration than an amorphous silicon thin film transistor. The polysilicon thin film transistor receives increasing attention in the market after laser technology is employed for fabricating the polysilicon thin film transistor under 600 centigrade degrees.

FIG. 1 is a schematic cross-sectional drawing of a conventional thin film transistor. Referring to FIG. 1, after a buffer layer 102 is formed on a substrate 100, a polysilicon layer 104 and a gate dielectric layer 106 are sequentially formed over the buffer layer 102. A gate layer 108 is formed on the gate dielectric layer 106. Thereafter, a source region 110 a and a drain region 110 b are formed using a doping method with a doping mask. A channel region 112 is formed under the gate layer 108. Leakage current and hot carrier effect can be avoided by forming lightly-doped-drain (LDD) regions 114 a and 114 b between the source region 110 a and the channel region 112 and between the drain region 110 b and the channel region 112. A source conductive layer 118 a and a drain conductive layer 118 b passing through the gate dielectric layer 106 and a dielectric layer 116 are electrically connected to the source region 110 a and the drain region 110 b, respectively.

In the above process, leakage current and hot carrier effect can be mitigated by the lightly-doped-drain (LDD) regions that are formed using an extra ion implanting process with an extra doping mask. In other words, the source region/drain region and the lightly-doped-drain (LDD) regions are formed using two steps of the ion implanting process with two different doping masks formed by different masking processes. Therefore, the process for fabricating the thin film transistor with the lightly-doped-drain (LDD) regions is complicated and time-consuming. The mismatch of the positioning of the different doping masks is resulted during the fabrication of the thin film transistor.

SUMMARY OF THE INVENTION

Accordingly, one object of the present invention is to provide a process for fabricating the thin film transistor with reduced processing steps.

Accordingly, one object of the present invention is to provide a thin film transistor with improved leakage current and hot carrier effect.

To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a method for fabricating the thin film transistor. A polysilicon layer and a gate dielectric layer are sequentially formed over a substrate. A patterned photoresist mask having a first portion and a second portion is formed over the gate dielectric layer, wherein the second portion has a thickness smaller than that of the first portion. The gate dielectric layer is patterned using an etching process with the patterned photoresist mask acting as an etching mask. The patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion is positioned at two sides of the third portion and has a thickness smaller than that of the third portion. An ion implanting process is performed with the patterned photoresist mask and the patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in the polysilicon layer under the fourth portion of the patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in the polysilicon layer under the third portion of the patterned gate dielectric layer. A channel region is positioned in the polysilicon layer under the third portion of the patterned gate dielectric layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region. Thereafter, the patterned photoresist mask is removed and then a gate layer is formed over the gate dielectric layer over the channel region.

To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a process for fabricating the thin film transistor. A polysilicon layer, a gate dielectric layer and a gate layer are sequentially formed over a substrate. A patterned photoresist mask having a first portion and a second portion is formed over the gate layer, wherein the first portion has a thickness smaller than that of the second portion. The gate layer and the gate dielectric layer are patterned using an etching process with the patterned photoresist mask acting as an etching mask. The patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion is positioned at two sides of the third portion and has a thickness smaller than that of the third portion. Thereafter, the patterned phosotresist mask is removed. An ion implanting process is performed with the patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in the polysilicon layer under the fourth portion of the patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in the polysilicon layer under the third portion of the patterned gate dielectric layer. A channel region is positioned in the polysilicon layer under the third portion of the patterned gate layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region. The above patterned photoresist layer can be removed after the ion implantation process.

To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a thin film transistor. The thin film transistor comprises a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a lightly-doped-drain (LDD) region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion of the patterned gate dielectric layer. The source region and the drain region are positioned in the polysilicon layer under the fourth portion of the patterned gate dielectric layer. The channel region is positioned in the polysilicon layer under the gate layer. The lightly-doped-drain (LDD) region is positioned in the polysilicon layer under the third portion of the patterned gate dielectric layer between the channel region and the source region or between the channel region and the drain region.

The source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the ion implanting process with only one patterned gate dielectric layer and only one patterned photoresist mask acting as a doping mask. Therefore, the method for fabricating a thin film transistor according to the present invention is efficient. The mismatch of positioning two different doping masks, frequently occurred in the prior art, can be avoided.

To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a process for fabricating the thin film transistor. A polysilicon layer, a gate dielectric layer and a gate layer are sequentially formed over a substrate. A patterned photoresist mask having a first portion and a second portion is formed over the gate layer, wherein the first portion has a thickness smaller than that of the second portion. The gate layer is patterned using an etching process with the patterned photoresist mask acting as an etching mask. The patterned gate layer has a fifth portion and a sixth portion, wherein the sixth portion has a thickness smaller than that of the fifth portion. Thereafter, the patterned photoresist layer is removed. A first ion implanting process for doping a source region and a drain region in the polysilicon layer is performed with the patterned photoresist mask and the patterned gate layer acting as a doping mask. Thereafter, the sixth portion of the patterned gate layer is removed. A second ion implanting process for doping the source region, the drain region and a lightly-doped-drain (LDD) region in the polysilicon layer is performed with the remaining patterned photoresist mask and the remaining patterned gate layer acting as a doping mask. A channel region is positioned in the polysilicon layer under the remaining patterned gate layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region. Thereafter, the patterned photoresist mask is removed. Further, the above patterned photoresist layer can be removed after the second ion implantation process.

The source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the photolithography process. Therefore, the method for fabricating a thin film transistor according to the present invention is efficient. The mismatch of the positioning of two different doping masks as often occurred in the prior art, can be avoided.

One or part or all of these and other features and advantages of the present invention will become readily apparent to those skilled in this art from the following description wherein there is shown and described a preferred embodiment of this invention, simply by way of illustration of one of the modes best suited to carry out the invention. As it will be realized, the invention is capable of different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic cross-sectional view of a conventional thin film transistor.

FIGS. 2A-2C are schematic cross-sectional views of a thin film transistor showing the steps a thin film transistor according to a first embodiment of the present invention.

FIGS. 3A-3B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention.

FIGS. 4A-4B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention.

FIGS. 5A-5B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention.

FIGS. 6A-6D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a second embodiment of the present invention.

FIGS. 7A-7B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention.

FIGS. 8A-8B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention.

FIGS. 9A-9B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.

FIGS. 13A-13D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a third embodiment of the present invention.

FIGS. 14A-14B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the third embodiment of the present invention.

FIGS. 15A-15B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the third embodiment of the present invention.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Various specific embodiments of the present invention are disclosed below, illustrating examples of various possible implementations of the concepts of the present invention. The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

First Embodiment

FIGS. 2A-2C are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a first embodiment of the present invention.

Referring to FIG. 2A, a polysilicon layer 204 and a gate dielectric layer 206 are sequentially formed over a substrate 200. The substrate 200 may be made of a transparent material, such as glass. The process for forming the polysilicon layer 204 includes forming an amorphous silicon layer (not shown) on the substrate 206, melting the amorphous silicon layer by an excimer-laser annealing (ELA) process, and then recrystallize the melted silicon layer. The gate dielectric layer 206 made of silicon oxide, silicon nitride, or silicon oxynitride, for example, can be formed using a chemical-vapor-deposition process. Alternatively, a buffer layer 202 made of silicon oxide, for example, can be formed over the substrate 200 before forming the polysilicon layer 204.

A patterned photoresist mask 208 having a first portion 210 a and a second portion 210 b is formed over the gate dielectric layer 206. The second portion 210 b is positioned at two sides of the first portion 210 a and has a thickness smaller than that of the first portion 210 a. The process of forming patterned photoresist mask 208 may include the following steps. First, an original photoresist layer (not shown) is formed over the gate dielectric layer 206. The original photoresist layer, such as positive photoresist, can be exposed to light with a mask 212 having a semi-transparent region 214 a, a transparent region 214 b and a light-blocking region 214 c. Afterwards, the original photoresist layer can be developed to form the patterned photoresist mask 208 having the first portion 210 a and the second portion 210 b. During exposing, the first portion 210 a is aligned with the light-blocking region 214 c of the mask 212, and the second portion 210 b is aligned with the semi-transparent region 214 a of the mask 212. The original photoresist layer that is aligned with the transparent region 214 b during exposing can be completely removed during developing.

Referring to 2B, the gate dielectric layer 206 a is patterned using an etching process with the patterned photoresist mask 208 acting as an etching mask. The patterned gate dielectric layer 206 a has a third portion 216 a and a fourth portion 216 b, wherein the fourth portion 216 b is positioned at two sides of the third portion 216 a and has a thickness smaller than that of the third portion 216 a. The gate dielectric layer 206 not covered by the patterned photoresist mask 208, during etching, can be partially removed to create the fourth portion 216 b. The gate dielectric layer 206 covered by the second portion 210 b of the patterned photoresist mask 208, during etching, can be retained or slightly removed and can be exposed thereafter. The gate dielectric layer 206 covered by the first portion 210 a of the patterned photoresist mask 208, is not removed during etching.

An ion implanting process 218 is performed with the patterned photoresist mask 208 and the patterned gate dielectric layer 206 a acting as a doping mask to form a source region 220 a and a drain region 220 b in the polysilicon layer 204 under the fourth portion 216 b of the patterned gate dielectric layer 206 a and to form lightly-doped-drain (LDD) regions 224 a and 224 b in the polysilicon layer 204 under the third portion 216 a of the patterned gate dielectric layer 206 a. A channel region 222 is configured in the polysilicon layer 204 under the third portion 216 a of the patterned gate dielectric layer 206 a, wherein the lightly-doped-drain (LDD) regions 224 a and 224 b are configured between the channel region 222 and the source region 220 a and between the channel region 222 and the drain region 220 b. After performing only one step of the ion implanting process 218, the regions with different dopant concentrations can be produced due to the patterned gate dielectric layer 206 a having different thicknesses. The channel region 222 is defined under the thickest portion of the doping mask which includes the third portion 216 a of the patterned gate dielectric layer 206 a and the patterned photoresist mask 208. The lightly-doped-drain (LDD) regions 224 a and 224 b can be formed under the second thickness portion of the doping mask which includes the third portion 216 a of the patterned gate dielectric layer 206 a. The source region 220 a and the drain region 220 b can be formed under the thinnest portion of the doping mask which includes the fourth portion 216 b of the patterned gate dielectric layer 206 a.

In one embodiment, under the condition that the gate dielectric layer 206 as shown in FIG. 2A is formed with a thickness of 1000 angstroms, and n-type dopants 218 such as phosphorous atoms are doped with a dopant concentration ranging from 1*10¹⁴ to 1*10¹⁶ atoms per square centimeter for fabricating a n-type polysilicon thin film transistor, the ion implanting process may provide a doping energy of 70 keV to 80 KeV, for example.

Thereafter, the patterned photoresist mask 208 is removed as shown in FIG. 2C and then a gate layer 226 is formed over the patterned gate dielectric layer 206 a over the channel region 222.

After the gate layer 226 is formed, a drain conductive layer and a source conductive layer will be formed. The detail will be described in the following. A dielectric layer 228 is formed over the substrate 200 and covers the gate layer 226 and the patterned gate dielectric layer 206 a. A source plug opening 230 a and a drain plug opening 230 b are formed passing through the dielectric layer 228 and the patterned gate dielectric layer 206 a and exposing the source region 220 a and the drain region 220 b. Afterwards, a conductive layer including a source conductive layer 232 a and a drain conductive layer 232 b is formed over the dielectric layer 228 and in the source plug opening 230 a and the drain plug opening 230 b. The source conductive layer 232 a is electrically connected to the source region 220 a. The drain conductive layer 232 b is electrically connected to the drain region 220 b.

The widths w1 and w2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are equivalent as shown in FIG. 2A, but, alternatively, they can be different in practice. Referring to FIG. 3A, the widths w1 and w2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are different. Therefore, as shown in FIG. 3B, asymmetric lightly-doped-drain (LDD) regions 224 a and 224 b with different widths are formed after the steps of etching the gate dielectric layer 206 and implanting ions. Besides, referring to FIG. 4A, the second portion 210 b is positioned at only one side of the first portion 210 a of the patterned photoresist mask 208. Accordingly, as shown in FIG. 4B, only one lightly-doped-drain (LDD) region 224 b is formed after the steps of etching the gate dielectric layer 206 and implanting ions.

Alternatively, referring to FIG. 5A, the gate dielectric layer 206 positioned over the polysilicon layer 204 can be formed from two layers 207 a and 207 b of gate dielectric material, wherein the two layers 207 a and 207 b may have different materials or a same material. In the step of patterning the gate dielectric layer 206, the gate dielectric layer 207 b not covered by the patterned photoresist layer 208 is partially etched until the gate dielectric layer 207 a is exposed, as shown in FIG. 5B.

Second Embodiment

In the following embodiment, the explanation for the elements having the same reference numbers recited in the above embodiment will be omitted.

FIGS. 6A-6D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a second embodiment of the present invention.

Referring to FIG. 6A, a polysilicon layer 204, a gate dielectric layer 206 and a gate layer 226 are sequentially formed over a substrate 200. Alternatively, a buffer layer 202 can be formed over the substrate 200 before forming the polysilicon layer 204.

A patterned photoresist mask 208 having a first portion 210 a and a second portion 210 b is formed over the gate layer 226. The second portion 210 b is positioned at two sides of the first portion 210 a and has a thickness smaller than that of the first portion 210 a. The process of forming patterned photoresist mask 208 may include the following steps. First, an original photoresist layer (not shown) is formed over the gate dielectric layer 206. The original photoresist layer, such as positive photoresist, can be exposed to light with a mask 212 having a semi-transparent region 214 a, a transparent region 214 b and a light-blocking region 214 c. Afterwards, the original photoresist layer can be developed to form the patterned photoresist mask 208 having the first portion 210 a and the second portion 210 b. During exposing, the first portion 210 a is aligned with the light-blocking region 214 c of the mask 212, and the second portion 210 b is aligned with the semi-transparent region 214 a of the mask 212. The original photoresist layer that is aligned with the transparent region 214 b during exposing can be completely removed during developing.

Referring to 6B, the gate layer 226 a is patterned using an etching process with the patterned photoresist mask 208 acting as an etching mask. The patterned gate layer 226 a has a fifth portion 300 a and a sixth portion 300 b, wherein the sixth portion 300 b is positioned at two sides of the fifth portion 300 a and has a thickness smaller than that of the fifth portion 300 a. The gate layer 226 not covered by the patterned photoresist mask 208, during etching, can be completely removed. The gate layer 226 covered by the second portion 210 b of the patterned photoresist mask 208, during etching, can be partially removed to create the sixth portion 300 b. The gate layer 226 covered by the first portion 210 a of the patterned photoresist mask 208, during etching, is not removed.

Thereafter, referring to FIG. 6C, the gate dielectric layer 206 a is patterned using an etching process with the patterned photoresist mask 208 and the patterned gate layer 226 a acting as an etching mask. During the step of etching gate dielectric layer 206, the sixth portion 300 b of the patterned gate layer 226 a is being removed. The patterned gate dielectric layer 206 a has a third portion 216 a and a fourth portion 216 b, wherein the fourth portion 216 b is positioned at two sides of the third portion 216 a and has a thickness smaller than that of the third portion 216 a. The gate dielectric layer 206 not covered by the patterned gate layer 226 a, during etching, can be partially removed to create the fourth portion 216 b. The gate dielectric layer 206 covered by the sixth portion 300 b of the patterned gate layer 226 a, during etching, can be retained or slightly removed and is exposed thereafter. The gate dielectric layer 206 covered by the fifth portion 300 a of the patterned gate layer 226 a, during etching, is not removed.

An ion implanting process is performed with the patterned photoresist mask 208, the patterned gate layer 226 b and the patterned gate dielectric layer 206 a acting as a doping mask to form a source region 220 a and a drain region 220 b in the polysilicon layer 204 under the fourth portion 216 b of the patterned gate dielectric layer 206 a and to form lightly-doped-drain (LDD) regions 224 a and 224 b in the polysilicon layer 204 under the third portion 216 a of the patterned gate dielectric layer 206 a. A channel region 222 is configured in the polysilicon layer 204 under the patterned gate layer 226 b, wherein the lightly-doped-drain (LDD) regions 224 a and 224 b are positioned between the channel region 222 and the source region 220 a and between the channel region 222 and the drain region 220 b.

Thereafter, as shown in FIG. 6D, the patterned photoresist mask 208 is removed. In one embodiment, the removal of the patterned photoresist layer 208 can be conducted after the patterning of the gate dielectric layer 206 a and before the ion implantation process. Further, in another embodiment, a drain conductive layer and a source conductive layer are formed after the removal of the patterned photoresist layer 208. The detail will be described in the following. After the patterned photoresist mask 208 is removed, a dielectric layer 228 is formed over the substrate 200 and covers the gate layer 226 and the patterned gate dielectric layer 206 a. A source plug opening 230 a and a drain plug opening 230 b are formed passing through the dielectric layer 228 and the patterned gate dielectric layer 206 a and exposing the source region 220 a and the drain region 220 b. Afterwards, a conductive layer including a source conductive layer 232 a and a drain conductive layer 232 b is formed over the dielectric layer 228 and in the source plug opening 230 a and the drain plug opening 230 b. The source conductive layer 232 a is electrically connected to the source region 220 a. The drain conductive layer 232 b is electrically connected to the drain region 220 b.

The widths w1 and w2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are equivalent as shown in FIG. 6A, but, alternatively, they can be different in practice. Referring to FIG. 7A, the widths w1 and w2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are different. Therefore, as shown in FIG. 7B, asymmetric lightly-doped-drain (LDD) regions 224 a and 224 b with different widths are formed after the steps of etching the gate dielectric layer 206 and implanting ions. Besides, referring to FIG. 8A, the second portion 210 b is positioned at only one side of the first portion 210 a of the patterned photoresist mask 208. Accordingly, as shown in FIG. 8B, only one lightly-doped-drain (LDD) region 224 b can be formed after the steps of etching the gate dielectric layer 206 and implanting ions.

Alternatively, referring to FIG. 9A, the gate dielectric layer 206 positioned over the polysilicon layer 204 can be formed from two layers 207 a and 207 b of gate dielectric material, wherein the two layers 207 a and 207 b may have different materials or a same material. In the step of patterning the gate dielectric layer 206, the gate dielectric layer 207 b not covered by the patterned photoresist layer 208 is partially etched until the gate dielectric layer 207 a is exposed, as shown in FIG. 9B.

The thin film transistor as shown in FIGS. 10, 11 and 12 can be fabricated employing the above first and second embodiments. The thin film transistor includes a substrate 500, a polysilicon layer 502, a patterned gate dielectric layer 504, a gate layer 506, a channel region 514, a source region 508 a, a drain region 508 b and lightly-doped-drain (LDD) regions 510 a and 510 b.

The polysilicon layer 502 is positioned over the substrate 500. The patterned gate dielectric layer 504 is positioned over the polysilicon layer 502. The patterned gate dielectric layer 504 has a third portion 512 a and a fourth portion 512 b, wherein the fourth portion 512 b is positioned at two sides of the third portion 512 a and has a thickness smaller than that of the third portion 512 a.

The gate layer 506 is positioned over the third portion 512 a of the patterned gate dielectric layer 504. The source region 508 a and the drain region 508 b are positioned in the polysilicon layer 502 under the fourth portion 512 b of the patterned gate dielectric layer 504. The channel region 514 is positioned in the polysilicon layer 502 under the gate layer 506. The lightly-doped-drain (LDD) regions 510 a and 510 b are positioned in the polysilicon layer 502 under the third portion 504 of the patterned gate dielectric layer 504 between the channel region 514 and the source region 508 a and between the channel region 514 and the drain region 508 b.

The thin film transistor further includes a dielectric layer 516, a source conductive layer 518 a and a drain conductive layer 518 b. The dielectric layer 516 covers the gate layer 506 and the patterned gate dielectric layer 504. The source conductive layer 518 a and the drain conductive layer 518 b are deposited over the dielectric layer 516 and pass through the dielectric layer 516 and the patterned gate dielectric layer 504 for electrically connecting with the source region 508 a and the drain region 508 b, respectively.

Alternatively, the thin film transistor further includes a buffer layer 520 positioned between the substrate 500 and the polysilicon layer 502.

Referring to FIG. 10, the lightly-doped-drain (LDD) region 510 a positioned between the channel region 514 and the source region 508 a has a width w3 equivalent to the width w4 of the lightly-doped-drain (LDD) region 510 b positioned between the channel region 514 and the drain region 508 b. Alternatively, referring to FIG. 11, the width w3 of the lightly-doped-drain (LDD) region 510 a positioned between the channel region 514 and the source region 508 a is different from the width w4 of the lightly-doped-drain (LDD) region 510 b positioned between the channel region 514 and the drain region 508 b. Alternatively, referring to FIG. 12, one of the lightly-doped-drain (LDD) region 510 a and 510 b can be formed between the channel region 514 and the source region 508 a or between the channel region 514 and the drain region 508 b.

According to the above method of the present invention, only one step of the ion implanting process is performed to produce a source region, a drain region and lightly-doped-drain (LDD) regions with different dopant concentrations due to a patterned gate dielectric layer having different thicknesses. The patterned gate dielectric layer is formed by a single step of the photolithography process and then by a single step of the etching process. The photolithography process is performed to produce a patterned photoresist mask with different thicknesses by means of a mask having a semi-transparent region. Therefore, the method of the present invention is easier than the conventional method. In addition, leakage current and hot carrier effect can be effectively improved by forming lightly-doped-drain (LDD) regions having a same width or different widths.

Third Embodiment

In the following embodiment, the explanation for the elements having the same reference numbers recited in the above embodiments will be skipped.

FIGS. 13A-13D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a third embodiment of the present invention.

Referring to FIG. 13A, a polysilicon layer 204, a gate dielectric layer 206 and a gate layer 226 are sequentially formed over a substrate 200. Alternatively, a buffer layer 202 can be formed over the substrate 200 before forming the polysilicon layer 204.

A patterned photoresist mask 208 having a first portion 210 a and a second portion 210 b is formed over the gate layer 226. The second portion 210 b is positioned at two sides of the first portion 210 a and has a thickness smaller than that of the first portion 210 a. The process of forming the patterned photoresist mask 208 over the gate layer 226 can be referred to the above discussion for the second embodiment, and the detailed explanation is omitted herein.

Referring to 13B, the gate layer 226 a is patterned using an etching process with the patterned photoresist mask 208 acting as an etching mask. The patterned gate layer 226 a has a fifth portion 300 a and a sixth portion 300 b, wherein the sixth portion 300 b is positioned at two sides of the fifth portion 300 a and has a thickness smaller than that of the fifth portion 300 a. The process of forming the patterned gate layer 226 a can be referred to the discussion of the above second embodiment, and the concerning explanation is omitted herein.

An ion implanting process for doping a source region 220 a and a drain region 220 b in the polysilicon layer 204 is performed with the patterned photoresist mask 208, the patterned gate layer 226 a and the gate dielectric layer 206 acting as a doping mask.

In one embodiment, under the condition that n-type dopants 600 such as phosphorous atoms are doped with a dopant concentration ranging from 1*10¹⁴ to 1*10¹⁶ atoms per square centimeter for fabricating a n-type thin film transistor, the ion implanting process may provide a doping energy of 70 to 80 keV, for example.

Thereafter, the sixth portion 300 b of the patterned gate layer 226 a is removed using an etching process. Another ion implanting process for doping the source region 220 a, the drain region 220 b and lightly-doped-drain (LDD) regions 224 a and 224 b in the polysilicon layer 204 is performed with the remaining patterned photoresist mask 208 and the remaining patterned gate layer 226 c acting as a doping mask. A channel region 222 is configured in the polysilicon layer 204 under the remaining patterned gate layer 226 c, wherein the lightly-doped-drain (LDD) regions 224 a and 224 b are positioned between the channel region 222 and the source region 220 a and between the channel region 222 and the drain region 220 b.

In another embodiment, under the condition that n-type dopants 602 such as phosphorous atoms are doped with a dopant concentration ranging from 1*10¹³ to 1*10¹⁵ atoms per square centimeter for fabricating a n-type thin film transistor, the ion implanting process may provide a doping energy of 70 to 80 keV, for example.

Thereafter, as shown in FIG. 13D, the patterned photoresist mask 208 is removed. In one embodiment, removing the patterned photoresist layer 208 is conducted after forming the patterned gate layer 226 and before performing ion implantation process 600. In another embodiment, after removing the patterned photoresist layer, a drain conductive layer and a source conductive layer are formed. The detail will be described in the following. After the patterned photoresist mask 208 is removed, a dielectric layer 228 is formed over the substrate 200 and covers the gate layer 226 and the patterned gate dielectric layer 206 a. A source plug opening 230 a and a drain plug opening 230 b are formed passing through the dielectric layer 228 and the patterned gate dielectric layer 206 a and exposing the source region 220 a and the drain region 220 b. Afterwards, a conductive layer including a source conductive layer 232 a and a drain conductive layer 232 b is formed over the dielectric layer 228 and in the source plug opening 230 a and the drain plug opening 230 b. The source conductive layer 232 a is electrically connected to the source region 220 a. The drain conductive layer 232 b is electrically connected to the drain region 220 b.

The widths w1 and w2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are equivalent as shown in FIG. 13A, but, alternatively, they can be different in practice. Referring to FIG. 14A, the widths w1 and w2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are different. Therefore, as shown in FIG. 14B, asymmetric lightly-doped-drain (LDD) regions 224 a and 224 b with different widths are formed after the steps of etching the gate dielectric layer 206 and implanting ions. Besides, referring to FIG. 15A, the second portion 210 b is positioned at only one side of the first portion 210 a of the patterned photoresist mask 208. Accordingly, as shown in FIG. 15B, only one lightly-doped-drain (LDD) region 224 b can be formed after the steps of etching the gate dielectric layer 206 and implanting ions.

According to the above method of the present invention, the source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the photolithography process. Therefore, the above method is more efficient than the conventional method. In addition, leakage current and hot carrier effect can be effectively improved by forming lightly-doped-drain (LDD) regions having a same width or different widths.

The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims. 

1. A thin film transistor, comprising: a substrate; a polysilicon layer disposed over said substrate; a patterned gate dielectric layer disposed over the polysilicon layer, said patterned gate dielectric layer having a third portion and a fourth portion, wherein said fourth portion has a thickness smaller than that of said third portion; a gate layer positioned over said third portion of said patterned gate dielectric layer; a source region configured in said polysilicon layer under said fourth portion of said patterned gate dielectric layer; a drain region configured in said polysilicon layer under said fourth portion of said patterned gate dielectric layer; a channel region configured in said polysilicon layer under said gate layer; and a lightly-doped-drain (LDD) region configured in said polysilicon layer under said third portion of said patterned gate dielectric layer, and between said channel region and said source region or between said channel region and said drain region.
 2. The transistor of claim 1, wherein said lightly-doped-drain (LDD) region is configured between said channel region and said source region and between said channel region and said drain region, and said lightly-doped-drain (LDD) region formed between said channel region and said source region has a same width as said lightly-doped-drain (LDD) region formed between said channel region and said drain region.
 3. The transistor of claim 1, wherein said lightly-doped-drain (LDD) region is positioned between said channel region and said source region and between said channel region and said drain region, and said lightly-doped-drain (LDD) region formed between said channel region and said source region has a width different from that of said lightly-doped-drain (LDD) region formed between said channel region and said drain region.
 4. The transistor of claim 1, further comprising: a dielectric layer covering said gate layer and said patterned gate dielectric layer; a source conductive layer positioned over said dielectric layer and passing through said dielectric layer and said patterned gate dielectric layer, said source conductive layer electrically connecting with said source region; and a drain conductive layer positioned over said dielectric layer and passing through said dielectric layer and said patterned gate dielectric layer, said drain conductive layer electrically connecting with said drain region.
 5. The transistor of claim 1, further comprising a buffer layer positioned between said substrate and said polysilicon layer. 